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FPGA学习--PWM产生
2014-04-20 19:39  

LIBRARY IEEE;                     
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_Arith.ALL;
USE IEEE.STD_LOGIC_Unsigned.ALL;

ENTITY pwm_logic IS
PORT(
clock:  IN STD_LOGIC; --系统输入时钟
duty_cycle: IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
pwm_en:  IN  STD_LOGIC; --PWM使能.
pwm_out: OUT STD_LOGIC --PWM输出
);
END;

ARCHITECTURE one OF pwm_logic  IS
SIGNAL pwm_out_io: STD_LOGIC;   --PWM输出
SIGNAL count:  STD_LOGIC_VECTOR(15 DOWNTO 0);--PWM内部计数器
BEGIN
pwm_out<=pwm_out_io;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN
  IF pwm_en ='1' THEN
   count<=count+1;
  END IF;
 END IF;
END PROCESS;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN
  IF pwm_en ='1' AND count(15 DOWNTO 12)<=duty_cycle THEN
   pwm_out_io<='1';
  ELSE
   pwm_out_io<='0';
  END IF;
 END IF;
END PROCESS;


END ;

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