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FPGA学习--步进电机控制
2014-04-20 19:36  

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_Arith.ALL;
USE IEEE.STD_LOGIC_Unsigned.ALL;

ENTITY step_moto IS
PORT(
clock:  IN STD_LOGIC;
key:  IN STD_LOGIC_VECTOR(1 DOWNTO 0);
led:  OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pwm_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END;

ARCHITECTURE one OF step_moto IS
SIGNAL pwm_out_r: STD_LOGIC_VECTOR(3  DOWNTO 0);
SIGNAL p_out_r:  STD_LOGIC_VECTOR(3  DOWNTO 0);
SIGNAL count:  STD_LOGIC_VECTOR(23 DOWNTO 0);--时钟分频计数器
SIGNAL counter:  STD_LOGIC_VECTOR(10 DOWNTO 0);--PWM内部计数器
SIGNAL cnt4:  STD_LOGIC_VECTOR(3  DOWNTO 0);--电机步进时序计数器
SIGNAL duty_cycle: STD_LOGIC_VECTOR(15 DOWNTO 0);--PWM占空比控制.
SIGNAL dir:   STD_LOGIC;--电机旋转方向控制
SIGNAL mode:  STD_LOGIC;--电机控制模式
SIGNAL dout1,dout2,dout3:STD_LOGIC_VECTOR(1 DOWNTO 0);--消抖寄存器
SIGNAL k_debounce: STD_LOGIC_VECTOR(1 DOWNTO 0);--按键消抖输出
SIGNAL key_edge: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL clk:   STD_LOGIC;--消抖动时钟
SIGNAL speed_clk: STD_LOGIC;--电机转动速度控制
SIGNAL pwm_clk:  STD_LOGIC;--PWM计数时钟.

BEGIN
led<=NOT (mode & dir);
pwm_out<=NOT pwm_out_r WHEN mode='1' ELSE p_out_r;
  
pwm_clk<='1' WHEN (count(6  DOWNTO 0)=B"111_1111")  ELSE '0';
clk<='1'    WHEN (count(15 DOWNTO 0)=X"FFFF")   ELSE '0';
speed_clk<='1' WHEN (count(23 DOWNTO 0)=X"FFFFFF")  ELSE '0';

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN
  count<=count+1;
 END IF;
END PROCESS;

   -------------------------------------------<<按键消抖部分
PROCESS (clock)
BEGIN
 IF RISING_EDGE(clock) THEN
  IF clk='1' THEN
   dout1<=key;
   dout2<=dout1;
   dout3<=dout2;
  END IF;
 END IF;
END PROCESS;

PROCESS (clock)--边延检测部份.
BEGIN
 IF RISING_EDGE(clock) THEN
  k_debounce<=dout1 OR dout2 OR dout3;--按键消抖输出.
 END IF;
END PROCESS;
key_edge<=NOT (dout1 OR dout2 OR dout3) AND k_debounce;


PROCESS(clock)--按键1
BEGIN
 IF RISING_EDGE(clock) THEN
  IF key_edge(0)='1' THEN
   dir<=NOT dir;
  END IF;
 END IF;
END PROCESS;

PROCESS(clock)--按键2
BEGIN
 IF RISING_EDGE(clock) THEN
  IF key_edge(1)='1' THEN
   mode<=NOT mode;
  END IF;
 END IF;
END PROCESS;

PROCESS (clock)--电机正/反转控制
BEGIN
 IF RISING_EDGE(clock) THEN
  IF speed_clk='1' THEN
   IF dir='1' THEN
    cnt4<=cnt4+1;
   ELSE
    cnt4<=cnt4-1;
   END IF;
  END IF;
 END IF;
END PROCESS;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN--PWM波计数器
  IF pwm_clk='1' THEN
   counter<=counter+1;
  END IF;
 END IF;
END PROCESS;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN--PWM A通道
  IF counter(3 DOWNTO 0)<duty_cycle(15 DOWNTO 12) THEN
   pwm_out_r(3)<='1';
  ELSE
   pwm_out_r(3)<='0';
  END IF;
 END IF;
END PROCESS;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN--PWM B 通道
  IF counter(3 DOWNTO 0)<duty_cycle(11 DOWNTO 8) THEN
   pwm_out_r(2)<='1';
  ELSE
   pwm_out_r(2)<='0';
  END IF;
 END IF;
END PROCESS;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN--PWM C 通道
  IF counter(3 DOWNTO 0)<duty_cycle(7 DOWNTO 4) THEN
   pwm_out_r(1)<='1';
  ELSE
   pwm_out_r(1)<='0';
  END IF;  
 END IF;
END PROCESS;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN--PWM D 通道
  IF counter(3 DOWNTO 0)<duty_cycle(3 DOWNTO 0) THEN
   pwm_out_r(0)<='1';
  ELSE
   pwm_out_r(0)<='0';
  END IF;  
 END IF;
END PROCESS;

PROCESS(clock)
BEGIN
 IF RISING_EDGE(clock) THEN
  IF speed_clk='1' THEN
   CASE cnt4(1 DOWNTO 0) IS
    WHEN "00"=> p_out_r<="1100";
    WHEN "01"=> p_out_r<="0110";
    WHEN "10"=> p_out_r<="0011";
    WHEN "11"=> p_out_r<="1001" ; 
   END CASE;
  END IF;
 END IF;
END PROCESS;

PROCESS(cnt4)--步进电机4细分控制PWM波参数表.
BEGIN
 CASE cnt4 IS
  WHEN "0000"=>duty_cycle<=X"f000";
  WHEN "0001"=>duty_cycle<=X"e600";
  WHEN "0010"=>duty_cycle<=X"bb00";
  WHEN "0011"=>duty_cycle<=X"6e00";
  WHEN "0100"=>duty_cycle<=X"0f00";
  WHEN "0101"=>duty_cycle<=X"0e60";
  WHEN "0110"=>duty_cycle<=X"0bb0";
  WHEN "0111"=>duty_cycle<=X"06e0";
  WHEN "1000"=>duty_cycle<=X"00f0";
  WHEN "1001"=>duty_cycle<=X"00e6";
  WHEN "1010"=>duty_cycle<=X"00bb";
  WHEN "1011"=>duty_cycle<=X"006e";
  WHEN "1100"=>duty_cycle<=X"000f";
  WHEN "1101"=>duty_cycle<=X"600e";
  WHEN "1110"=>duty_cycle<=X"B00b";
  WHEN "1111"=>duty_cycle<=X"E006";
  END CASE;
END PROCESS;

END;

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