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FPGA学习--分频器的设计
2014-04-19 22:33  

一、2的整数次幂的分频,占空比为1:1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY clkdiv IS
PORT(clk : IN STD_LOGIC;
clk_div2 : OUT STD_LOGIC;
clk_div4 : OUT STD_LOGIC;
clk_div8 : OUT STD_LOGIC;
clk_div16 : OUT STD_LOGIC);
END clk_div;

ARCHITECTURE rtl OF clk_div IS
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF (clk’event AND clk=’1’) THEN
IF(count=”1111”) THEN
Count <= (OTHERS =>’0’);
ELSE
Count <= count +1;
END IF ;
END IF ;
END PROCESS;

clk_div2 <= count(0);
clk_div4 <= count(1);
clk_div8 <= count(2);
clk_div16 <= count(3);
END rtl;

二、任意整数分频,6分频的分频器,占空比为1:1

ENTITY clkdiv IS
PORT(clk : IN STD_LOGIC;
clk_div6 : OUT STD_LOGIC);
END clk_div;

ARCHITECTURE rtl OF clk_div IS
SIGNAL count : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL clk_temp : STD_LOGIC;

BEGIN
PROCESS(clk)
BEGIN
IF (clk’event AND clk=’1’) THEN
IF(count=”10”) THEN
count <= (OTHERS =>’0’);
clk_temp <=NOT clk_temp;
ELSE
count <= count +1;
END IF ;
END IF ;
END PROCESS;

clk_div6 <= clk_temp;
END rtl;

三、占空比可调的分频器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY clkdiv IS
PORT(clk : IN STD_LOGIC;
clk_div16 : OUT STD_LOGIC);
END clk_div;

ARCHITECTURE rtl OF clk_div IS
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF (clk’event AND clk=’1’) THEN
IF(count=”1111”) THEN
Count <= (OTHERS =>’0’);
ELSE
Count <= count +1;
END IF ;
END IF ;
END PROCESS;

PROCESS(clk)
BEGIN
IF (clk’event AND clk=’1’) THEN
IF(count=”1111”) THEN                 --改变IF的条件可实现不同占空比
Clk_div16 <= ‘1’;
ELSE
Clk_div <= ‘0’;
END IF ;
END IF ;
END PROCESS;
END rtl;

四、数控分频

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DVF IS
    PORT (   CLK  : IN STD_LOGIC;
               D  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             FOUT : OUT STD_LOGIC  );
END;
ARCHITECTURE one OF DVF IS
    SIGNAL   FULL : STD_LOGIC;
BEGIN
  P_REG: PROCESS(CLK)
   VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
   BEGIN           
      IF CLK’EVENT AND CLK = ’1’ THEN
            IF CNT8 = "11111111" THEN   
            CNT8 := D;      --当CNT8计数计满时,输入数据D被同步预置给计数器CNT8
              FULL <= ’1’; --同时使溢出标志信号FULL输出为高电平               
                ELSE   CNT8 := CNT8 + 1;  --否则继续作加1计数
                        FULL <= ’0’;        --且输出溢出标志信号FULL为低电平    
            END IF;
      END IF;
    END PROCESS P_REG ;
   P_DIV: PROCESS(FULL)
     VARIABLE CNT2 : STD_LOGIC;
   BEGIN
   IF FULL’EVENT AND FULL = ’1’ THEN  
     CNT2 := NOT CNT2; --如果溢出标志信号FULL为高电平,D触发器输出取反
         IF CNT2 = ’1’ THEN  FOUT <= ’1’; ELSE FOUT <= ’0’;
        END IF;
   END IF;
    END PROCESS P_DIV ;
END; 

五、小数分频器设计

    设计原理:小数分频的基本原理是采用脉冲吞计数器和锁相环先设计两个不同分频比的整数分频器,然后通过控制单位时间内两种分频比出现的不同次数来获得所需要的小数分频值。由于分频器的分频值不断改变,因此分频后得到的信号抖动比较大,实际应用不常用。半数分频稳定,经常会用。下面是一个2.5分频器的程序。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fenpin is
generic(dwidth:integer:=3);
port(clkin:in std_logic;
     set:in std_logic_vector(dwidth downto 0);
     clkout:buffer std_logic);
end;
architecture rt1 of fenpin is
signal clk,div2:std_logic;
signal count:integer range dwidth downto 0;
begin
clk<=clkin xor div2;
process(clk)
begin
if(clk'event and clk='1') then
if (count=0) then
count<= to_integer(unsigned(set))-1;
clkout<='1';
else
count<=count-1;
clkout<='0';
end if;
end if;
end process;
process(clkout)
begin
if(clkout'event and clkout='1') then
div2<=not div2;
end if;
end process;
end rt1;

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